Memory has many uses in modern integrated circuitry. One known type of memory cell is a static memory cell, such as may be utilized in static random access memory (SRAM). A static memory cell is characterized by operation in one of two mutually-exclusive and self-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a “high” voltage to indicate a “set” operating state. The memory cell output produces a “low” voltage to indicate a “reset” operating state. A low or reset output voltage usually represents a binary value of zero, while a high or set output voltage represents a binary value of one.
A static memory cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The operation of a static memory cell is in contrast to other types of memory cells, such as dynamic memory cells, which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods.
A dynamic memory cell has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, while static memory cells comprise many more transistors (for instance, some static memory cells comprise six transistors). Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along generally different paths than has the design of dynamic memories.
A static memory cell 10 is illustrated in FIG. 1. Static memory cell 10 generally comprises first and second inverters 12 and 14 which are cross-coupled to form a bistable flip-flop. Inverters 12 and 14 are formed by first and second n-channel pulldown (driver) transistors N1 and N2, and first and second p-channel pullup (load) transistors P1 and P2. The pulldown transistors may be referred to as pulldown devices (or driver devices), and the pullup transistors may be referred to as pullup devices (or load devices).
Driver transistors N1 and N2 have respective source regions 66 and 68 tied to a low reference or circuit supply voltage, labelled Vss, and typically referred to as “ground.” Driver transistors N1 and N2 have respective drain regions 64 and 62, and respective gates 65 and 63. Load transistors P1 and P2 have respective source regions 78 and 80 tied to a high reference or circuit supply voltage, labelled Vcc, and have respective drain regions 70 and 72 tied to the drain regions 64 and 62, respectively, of the corresponding driver transistors N1 and N2. A gate 75 of the load transistor P1 is connected to the gate 65 of the driver transistor N1. A gate 73 of the load transistor P2 is connected to the gate 63 of the driver transistor N2.
Inverter 12 has an inverter output 20 from the drain region 64 of the driver transistor N1. Similarly, inverter 14 has an inverter output 22 from the drain region 62 of driver transistor N2. Inverter 12 has an inverter input 76 to the gate 65 of the driver transistor N1. Inverter 14 has an inverter input 74 to the gate 63 of the driver transistor N2.
The inputs and outputs of inverters 12 and 14 are cross-coupled to form a flip-flop having a pair of complementary two-state outputs. Specifically, inverter output 20 is coupled to inverter input 74 via a line 26, and inverter output 22 is coupled to inverter input 76 via a line 24. In this configuration, inverter outputs 20 and 22 form the complementary two-state outputs of the flip-flop.
A memory flip-flop, such as that described, typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 30 and 32, are used to selectively address and access individual memory elements within the array. Access transistor 30 has one active terminal 58 (i.e., a source/drain region) connected to the cross-coupled inverter output 20. Access transistor 32 has one active terminal 60 (i.e., a source/drain region) connected to the cross-coupled inverter output 22. A pair of comparative bitlines 34 and 36 are connected to the remaining active terminals (i.e., the remaining source/drain regions) 56 and 54 of access transistors 30 and 32, respectively; and such comparative bitlines extend to circuitry 37 utilized for read/write operations associated with the static memory cell (such circuitry may comprise any suitable components, including, for example, logic, CMOS, a sense amplifier, drivers, etc.). A wordline 38 is connected to gates 31 and 33 of access transistors 30 and 32, respectively. In the illustrated embodiment, access transistors 30 and 32 would typically be n-channel transistors.
Reading static memory cell 10 requires activating wordline 38 to connect inverter outputs 20 and 22 to comparative bitlines 34 and 36. Writing to static memory cell 10 requires complementary logic voltage on comparative bitlines 34 and 36 with wordline 38 activated. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
In semiconductor processing, there is a continuing desire to make circuits denser, and to place components closer and closer together to reduce the size of circuits. It would be desirable to develop improved architectures for static memory which are suitable for utilization in highly integrated applications.